💻Which step does Make take when it is invoked on a target?

Figure 1: An example photo showing the Makefile contents 📂.

1. Make determines whether the component exists.

2. Examine the component's dependency hierarchy.

3. Conduct a bottom-up search through the dependencies while comparing the timestamp between the object and their dependencies.

4. If a dependency has been modified or rebuilt after the latest update on the object, the object will be rebuilt.

💫Make build command example

$(CC) -c -o $@ $<

$@ represents the target and $< represents the first dependency.

🤔What if Make changed its default compiler?

💡Make use of the "CC" variable as its default compiler.

🚀When invoking the following code snippet, Make override the default "CC" variable value to use "ICC" instead:

make CC=icc

💭What are the potential consequences?

1. The Make file contents might be compatible with the new "ICC" compiler. This will cause unexpected code behaviours.

2. Previous flags and configurations are not adaptable to the new compiler.

3. Incompatible libraries issue - "ICC" links different libraries to "CC".

4. Differences in defining bugs could lead to the code raising different warnings and issues.

💭What happens if a dependency is removed from the Makefile?

1. Missing dependency could cause compilation errors when the Makefile doesn't have the build script to create the dependency from scratch.

2. Even if the Makefile builds the dependency, the build script is custom and could produce unpredictable behaviours.

3. If the dependency is a header file, there may be errors from unresolved symbols.